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VTS-ID/8249
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URL: http://vts.uni-ulm.de/doc.asp?id=8249
URN: urn:nbn:de:bsz:289-vts-82498
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| Titel | A 60 GHz, multi-Gbps down-converter IC in an 80 GHz fT SiGe technology |
| Autor / Hrsg. |
Liu, Gang
|
| Dokumentart | Dissertation |
| Institution | Universität Ulm. Fakultät für Ingenieurwissenschaften und Informatik |
| DDC-Sachgruppe |
Engineering & allied operations (ddc:620)
|
| Schlagwörter (): Schlagwortschema |
Down-converter IC (custom)
Konverter <Elektronik> (SWD) Multi-Gbps (custom) SiGe technology (custom) Wireless communication systems (LCSH) 60 GHz (custom) |
| Sprache | englisch |
| Jahr der Erstellung | 2012 |
| Signatur | W: W-H 13.088 |
| VTS-Veröffentlichung | 16.11.2012 |
| Statistik |
156 Zugriffe seit 16.11.2012
|
| Abstract | This dissertation describes the design and characterization of low-cost 60 GHz down-converter ICs and modules for short-range multi-gigabit per second wireless communications. Low-cost semiconductor technology and packaging techniques are used for the IC and module design, making the module also suited for small volume production. The down-converter IC, consisting of a down-converting mixer, a VCO plus frequency doubler and an analog PLL, is realized in an 80 GHz SiGe HBT technology. The high ratio of operating frequency to fT/fmax makes the circuit design very challenging, requiring each building blocks to be optimized carefully. The design, simulation and optimization of the individual circuit blocks, as well as experimental results are discussed in detail in this dissertation. The complete IC achieves 5 dB conversion gain and more than 10 GHz IF bandwidth, covering the complete 60 GHz ISM band. The PLL achieves state-of-art tuning range and phase noise performance. The down-converter IC is packaged in a module with coaxial input and output. Low-cost wire-bonding techniques are implemented for the IC-to-board interconnect. To compensate the influence of the bondwires, an "L-C-L" compensating structure has been adopted, which shows 0.3 dB insertion loss at 60 GHz. The design, simulation and test results of the bondwire interconnect are discussed in detail in this dissertation. Different modules have been compared and the packaging related issues are discussed. The packaged modules are successfully implemented in a 60 GHz wireless system with BPSK modulation. Error-free transmission up to 2 Gbit/s (limited by the transmitter) has been achieved for over a distance of 1 meter. The experimental test setup and measurement results are also shown in this dissertation. This thesis work is the first reported 60 GHz receiver front-end using such low-cost semiconductor technology and packaging techniques. |
Dateien
Anzahl der Teildokumente: 1
| Teildokument | Format | Zertifikat / Hash |
|---|---|---|
| vts_8249_12085.pdf Dateigröße: 7292 kByte 139 S. | application/pdf | PGP-Signatur: DH/DSS Zertifikat MD5-Hash: c9de4ca3c055fc287de74dc4108d1d8c |